Matsushita and Intel started mass-producing 45 nm chips in late 2007, and AMD started production of 45 nm chips in late 2008, while IBM, Infineon, Samsung, and Chartered Semiconductor have already completed a common 45 nm process platform. At the end of 2008, SMIC was the first China-based semiconductor company to move to 45 nm, having licensed the bulk 45 nm process from IBM. In 2008, TSMC moved on to a 40nm process.
Many critical feature sizes are smaller than the wavelength of light used for lithography (i.e., 193 nm and 248 nm). A variety of techniques, such as larger lenses, are used to make sub-wavelength features. Double patterning has also been introduced to assist in shrinking distances between features, especially if dry lithography is used. It is expected that more layers will be patterned with 193 nm wavelength at the 45 nm node. Moving previously loose layers (such as Metal 4 and Metal 5) from 248 nm to 193 nm wavelength is expected to continue, which will likely further drive costs upward, due to difficulties with 193 nm photoresists.
Chipmakers have initially voiced concerns about introducing new high-? materials into the gate stack, for the purpose of reducing leakage current density. As of 2007, however, both IBM and Intel have announced that they have high-? dielectric and metal gate solutions, which Intel considers to be a fundamental change in transistor design.NEC has also put high-? materials into production.
In 2004, TSMC demonstrated a 0.296 square micrometer 45 nm SRAM cell. In 2008, TSMC moved on to a 40 nm process.
In January 2006, Intel demonstrated a 0.346 square micrometers 45 nm node SRAM cell.
In April 2006, AMD demonstrated a 0.370 square micrometer 45 nm SRAM cell.
Intel shipped its first 45nm processor, the Xeon 5400 series, in November 2007.
Many details about Penryn appeared at the April 2007 Intel Developer Forum. Its successor is called Nehalem. Important advances include the addition of new instructions (including SSE4, also known as Penryn New Instructions) and new fabrication materials (most significantly a hafnium-based dielectric).
At IEDM 2007, more technical details of Intel's 45 nm process were revealed.
Since immersion lithography is not used here, the lithographic patterning is more difficult. Hence, a line-cutting double patterning method is used explicitly for this 45 nm process. Also, the use of high-? dielectric dielectrics is introduced for the first time, to address gate leakage issues. For the 32 nm node, immersion lithography will begin to be used by Intel.
160 nm gate pitch (73% of 65 nm generation)
200 nm isolation pitch (91% of 65 nm generation) indicating a slowing of scaling of isolation distance between transistors
Extensive use of dummy copper metal and dummy gates
35 nm gate length (same as 65 nm generation)
1 nm equivalent oxide thickness, with 0.7 nm transition layer
Gate-last process using dummy polysilicon and damascene metal gate
Squaring of gate ends using a second photoresist coating
9 layers of carbon-doped oxide and Cu interconnect, the last being a thick "redistribution" layer
1.07 mA/µm pFET drive current, 51 % faster than 65 nm generation, with higher hole mobility due to increase from 23 % to 30 % Ge in embedded SiGe stressors
In a recent Chipworks reverse-engineering, it was disclosed that the trench contacts were formed as a "Metal-0" layer in tungsten serving as a local interconnect. Most trench contacts were short lines oriented parallel to the gates covering diffusion, while gate contacts where even shorter lines oriented perpendicular to the gates.
It was recently revealed that both the Nehalem and Atom microprocessors used SRAM cells containing eight transistors instead of the conventional six, in order to better accommodate voltage scaling. This resulted in an area penalty of over 30%.