List of Device Bandwidths
Browse the List of Device Bandwidths below, , or join the discussion on this topic. Add List of Device Bandwidths to your topic list for future reference or share this resource on social media.
List of Device Bandwidths

This is a list of interface bit rates, is a measure of information transfer rates, or digital bandwidth capacity, at which digital interfaces in a computer or network can communicate over various kinds of buses and channels. The distinction can be arbitrary between a computer bus, often closer in space, and larger telecommunications networks. Many device interfaces or protocols (e.g., SATA, USB, SAS, PCIe) are used both inside many-device boxes, such as a PC, and one-device-boxes, such as a hard drive enclosure. Accordingly, this page lists both the internal ribbon and external communications cable standards together in one sortable table.

Factors limiting actual performance, criteria for real decisions

Most of the listed rates are theoretical maximum throughput measures; in practice, the actual effective throughput is almost inevitably lower in proportion to the load from other devices (network/bus contention), physical or temporal distances, and other overhead in data link layer protocols etc. The maximum goodput (for example, the file transfer rate) may be even lower due to higher layer protocol overhead and data packet retransmissions caused by line noise or interference such as crosstalk, or lost packets in congested intermediate network nodes. All protocols lose something, and the more robust ones that deal resiliently with very many failure situations tend to lose more maximum throughput to get higher total long term rates.

Device interfaces where one bus transfers data via another will be limited to the throughput of the slowest interface, at best. For instance, SATA revision 3.0 (6 Gbit/s) controllers on one PCI Express 2.0 (5 Gbit/s) channel will be limited to the 5 Gbit/s rate and have to employ more channels to get around this problem. Early implementations of new protocols very often have this kind of problem. The physical phenomena on which the device relies (such as spinning platters in a hard drive) will also impose limits; for instance, no spinning platter shipping in 2009 saturates SATA revision 2.0 (3 Gbit/s), so moving from this 3 Gbit/s interface to USB 3.0 at 4.8 Gbit/s for one spinning drive will result in no increase in realized transfer rate.

Contention in a wireless or noisy spectrum, where the physical medium is entirely out of the control of those who specify the protocol, requires measures that also use up throughput. Wireless devices, BPL, and modems may produce a higher line rate or gross bit rate, due to error-correcting codes and other physical layer overhead. It is extremely common for throughput to be far less than half of theoretical maximum, though the more recent technologies (notably BPL) employ preemptive spectrum analysis to avoid this and so have much more potential to reach actual gigabit rates in practice than prior modems.

Another factor reducing throughput is deliberate policy decisions made by Internet service providers that are made for contractual, risk management, aggregation saturation, or marketing reasons. Examples are rate limiting, bandwidth throttling, and the assignment of IP addresses to groups. These practices tend to minimize the throughput available to every user, but maximize the number of users that can be supported on one backbone.

Furthermore, chips are often not available in order to implement the fastest rates. AMD, for instance, does not support the 32-bit HyperTransport interface on any CPU it has shipped as of the end of 2009. Additionally, WiMAX service providers in the US typically support only up to 4 Mbit/s as of the end of 2009.

Choosing service providers or interfaces based on theoretical maxima is unwise, especially for commercial needs. A good example is large scale data centers, which should be more concerned with price per port to support the interface, wattage and heat considerations, and total cost of the solution. Because some protocols such as SCSI and Ethernet now operate many orders of magnitude faster than when originally deployed, scalability of the interface is one major factor, as it prevents costly shifts to technologies that are not backward compatible. Underscoring this is the fact that these shifts often happen involuntarily or by surprise, especially when a vendor abandons support for a proprietary system.


Prefixes for multiples of
bits (bit) or bytes (B)
Value SI
1000 103 k kilo
10002 106 M mega
10003 109 G giga
10004 1012 T tera
10005 1015 P peta
10006 1018 E exa
10007 1021 Z zetta
10008 1024 Y yotta
1024 210 Ki kibi K kilo
10242 220 Mi mebi M mega
10243 230 Gi gibi G giga
10244 240 Ti tebi -
10245 250 Pi pebi -
10246 260 Ei exbi -
10247 270 Zi zebi -
10248 280 Yi yobi -

By convention, bus and network data rates are denoted either in bits per second (bit/s) or bytes per second (B/s). In general, parallel interfaces are quoted in B/s and serial in bit/s. The more commonly used is shown below in bold type.

On devices like modems, bytes may be more than 8 bits long because they may be individually padded out with additional start and stop bits; the figures below will reflect this. Where channels use line codes (such as Ethernet, Serial ATA and PCI Express), quoted rates are for the decoded signal.

The figures below are simplex data rates, which may conflict with the duplex rates vendors sometimes use in promotional materials. Where two values are listed, the first value is the downstream rate and the second value is the upstream rate.

All quoted figures are in metric decimal units. Note that these aren't the traditional binary prefixes for memory size. These decimal prefixes have long been established in data communications. This occurred before 1998 when IEC and other organizations introduced new binary prefixes and attempted to standardize their use across all computing applications.


The figures below are grouped by network or bus type, then sorted within each group from lowest to highest bandwidth; gray shading indicates a lack of known implementations.

As stated above, all quoted bandwidths are for each direction. Therefore for duplex interfaces (capable of simultaneous transmission both ways), the stated values are simplex (one way) speeds, rather than total upstream+downstream.

Time Signal Station to Radio Clock

Technology Max. rate Year
IRIG and related 1 bit/s ~0.125 characters/s[1][2] ?

Teletypewriter (TTY) or telecommunications device for the deaf (TDD)

Technology Max. rate Year
TTY (V.18) 6 characters/s[3] ?
TTY (V.18) 6.6 characters/s ?
NTSC Line 21 Closed Captioning ~100 characters/s ?

Modems (narrowband and broadband)

Narrowband (POTS: 4 kHz channel)

Technology Rate Rate ex. overhead Year
Morse code (skilled operator) [4] [5] 1844
Teleprinter (50 baud) 1940x
Modem 110 baud (Bell 101) (~10 cps)[6] 1959
Modem 300 (300 baud; Bell 103 or V.21) (~30 cps)[6] 1962[7]
Modem 1200/75 (600 baud; V.23) (~120 cps)[6] 1964(?)[8]
Modem 1200 (600 baud; Vadic VA3400, Bell 212A, or V.22) (~120 cps)[6] 1976
Modem 2400 (600 baud; V.22bis) [6] 1984[8]
Modem 4800/75 (1600 baud; V.27ter) [6] 1976[8]
Modem 9600 (2400 baud; V.32) [6] 1984[8]
Modem 14.4 (2400 baud; V.32bis) [6] 1991[7]
Modem 28.8 (3200 baud; V.34-1994) [6] 1994
Modem 33.6 (3429 baud; V.34-1996/98) [6] 1996[8]
Modem 56k (8000/3429 baud; V.90) [9] 1998
Modem 56k (8000/8000 baud; V.92) [9] 2001
Modem data compression (variable; V.92/V.44) [9] 2000[8]
ISP-side text/image compression (variable) 1998[8]
ISDN Basic Rate Interface (single/dual channel) [10] 1986[11]
IDSL (dual ISDN + 16 kbit/s data channels) 2000[12]

Broadband (hundreds of kHz to GHz wide)

Technology Rate Rate ex. overhead Year
ADSL (G.lite) 1998
HDSL ITU G.991.1 a.k.a. DS1 1998[13]
SHDSL ITU G.991.2 2001
ADSL (G.dmt) ITU G.992.1 1999
ADSL2 ITU G.992.3 2002
ADSL2+ ITU G.992.5 2003
DOCSIS 1.0[14] (cable modem) 1997
DOCSIS 2.0[15] (cable modem) 2002
VDSL ITU G.993.1 2001
VDSL2 ITU G.993.2 2006
Uni-DSL 2006
VDSL2 ITU G.993.2 Amendment 1 (11/15) 2015
BPON (G.983) fiber optic service 2005[16] ITU G.9700 2014
EPON (802.3ah) fiber optic service 2008
DOCSIS 3.0[17] (cable modem) 2006
GPON (G.984) fiber optic service 2008[18]
DOCSIS 3.1[19] (cable modem) 2013
10G-PON (G.987) fiber optic service 2012[20]
XGS-PON (G.9807.1) fiber optic service 2016
DOCSIS 3.1 Full Duplex (cable modem) 2017
NG-PON2 (G.989) fiber optic service 2015[21]

Mobile telephone interfaces

Technology Download rate Upload rate Year
GSM CSD (2G) [22]
GPRS (2.5G)
CDMA2000 1×RTT
EDGE (2.75G) (type 1 MS) 2002
EDGE (type 2 MS)
EDGE Evolution (type 1 MS)
EDGE Evolution (type 2 MS)
1×EV-DO rev. 0
1×EV-DO rev. A
1×EV-DO rev. B
HSPA (3.5G)
4×EV-DO Enhancements (2×2 MIMO)
HSPA+ (2×2 MIMO)
15×EV-DO rev. B
UMB (2×2 MIMO)
LTE (2×2 MIMO) 2004
UMB (4×4 MIMO)
EV-DO rev. C
LTE (4×4 MIMO)
5G ? ? ? ? ?

Wide area networks

Technology Rate Year
56k line 1990
G.lite (a.k.a. ADSL Lite)
DS1 / T1 (and ISDN Primary Rate Interface) 1990
E1 (and ISDN Primary Rate Interface)
LR-VDSL2 (4 to 5 km [long-]range) (symmetry optional)
Satellite Internet[25]
DOCSIS 1.0 (cable modem)[14] 1997
DOCSIS 2.0 (cable modem)[15] 2002
DS3 / T3 ('45 Meg')
STS-1 / OC-1 / STM-0
VDSL (symmetry optional)
OC-3 / STM-1
VDSL2 (symmetry optional)
OC-12 / STM-4
DOCSIS 3.0 (cable modem)[17] 2006
OC-48 / STM-16
OC-192 / STM-64
10 Gigabit Ethernet WAN PHY
DOCSIS 3.1 (cable modem) 2013
DOCSIS 3.1 Full Duplex (cable modem) 2017
OC-768 / STM-256
OC-1536 / STM-512
OC-3072 / STM-1024

Local area networks

Technology Rate Year
LocalTalk 1988
Econet 1981
Omninet 1980
IBM PC Network 1985
ARCNET (Standard) 1977
Chaosnet (Original) 1971
Token Ring (Original) 1985
Ethernet (10BASE-X) 1980 (1985 IEEE Standard)
Token Ring (Later) 1989
ARCnet Plus 1992
TCNS 1993?
100VG 1995
Token Ring IEEE 802.5t
Fast Ethernet (100BASE-X) 1995
MoCA 1.0[26]
MoCA 1.1[26]
HomePlug AV 2005
FireWire (IEEE 1394) 400[27][28] 1995
IEEE 1901 2010
Token Ring IEEE 802.5v 2001
Gigabit Ethernet (1000BASE-X) 1998
Reflective memory or RFM2 (1.25 µs latency) 2017
Myrinet 2000
Infiniband SDR 1×[29] 2001
RapidIO Gen1 1× 2000
2.5 Gigabit Ethernet (2.5GBASE-T) 2016
Quadrics QsNetI
Infiniband DDR 1×[29] 2005
RapidIO Gen2 1× 2008
5 Gigabit Ethernet (5GBASE-T) 2016
Infiniband QDR 1×[29] 2007
Infiniband SDR 4×[29]
Quadrics QsNetII
RapidIO Gen1 4x
RapidIO Gen2 2x 2008
10 Gigabit Ethernet (10GBASE-X) 2002-2006
Myri 10G
Infiniband FDR-10 1×[30]
NUMAlink 3 2004
Infiniband FDR 1×[30] 2011
Infiniband DDR 4×[29] 2005
RapidIO Gen2 4x 2008
Scalable Coherent Interface (SCI) Dual Channel SCI, x8 PCIe
Infiniband SDR 12×[29]
RapidIO Gen4 1× 2016
Infiniband EDR 1×[30] 2014
25 Gigabit Ethernet (25GBASE-X) 2016
NUMAlink 4 2004
Infiniband QDR 4×[29] 2007
RapidIO Gen2 8x 2008
40 Gigabit Ethernet (40GBASE-X) 4× 2010
Infiniband FDR-10 4×[30]
Infiniband DDR 12×[29] 2005
Infiniband HDR 1×[31] [30] 2017
NUMAlink 6 2012
Infiniband FDR 4×[30] 2011
RapidIO Gen2 16× 2008
Infiniband QDR 12×[29] 2007
Infiniband EDR 4×[30] 2014
100 Gigabit Ethernet (100GBASE-X) 10×/4× 2010/2018
Omni-Path 2015
Infiniband FDR-10 12×[30]
NUMAlink 7 2014
Infiniband FDR 12×[30] 2011
Infiniband HDR 4×[31] [30] 2017
200 Gigabit Ethernet (200GBASE-X) 2017
Infiniband EDR 12×[30] 2014
400 Gigabit Ethernet (400GBASE-X) 2017
Infiniband HDR 12×[31] [30] 2017

Wireless networks

802.11 networks in infrastructure mode are half-duplex; all stations share the medium. In infrastructure or access point mode, all traffic has to pass through an Access Point (AP). Thus, two stations on the same access point that are communicating with each other must have each and every frame transmitted twice: from the sender to the access point, then from the access point to the receiver. This approximately halves the effective bandwidth.

802.11 networks in ad hoc mode are still half-duplex, but devices communicate directly rather than through an access point. In this mode all devices must be able to "see" each other, instead of only having to be able to "see" the access point.

Standard Rate Year
Classic WaveLAN 1988
IEEE 802.11 1997
RONJA (full duplex) 2001
IEEE 802.11a 1999
IEEE 802.11b 1999
IEEE 802.11g 2003
IEEE 802.16 (WiMAX) 2004
IEEE 802.11g with Super G by Atheros 2003
IEEE 802.11g with 125 High Speed Mode by Broadcom 2003
IEEE 802.11g with Nitro by Conexant 2003
IEEE 802.11n (aka Wi-Fi 4) 2009
IEEE 802.11ac (aka Wi-Fi 5) 2012
IEEE 802.11ad 2011
IEEE 802.11ax (aka Wi-Fi 6) 2019

Wireless personal area networks

Technology Rate Year
802.15.4 (2.4 GHz)
Bluetooth 1.1 2002
Bluetooth 2.0+EDR 2004
Bluetooth 3.0 2009
Bluetooth 4.0 2010
Bluetooth 5.0 2016

Computer buses

Main buses

Technology Rate Year
I²C 1992 (standardized)
Apple II series (incl. Apple IIGS) 8-bit/1 MHz [32][33] 1977
SS-50 Bus 8-bit/1(?) MHz 1975
STD-80 8-bit/8 MHz
ISA 8-Bit/4.77 MHz 0 W/S: every 4 clocks 8 bits
1 W/S: every 5 clocks 8 bits
0 W/S: every 4 clocks 1 byte
1 W/S: every 5 clocks 1 byte
1981 (created)
STD-80 16-bit/8 MHz
I3C (HDR mode)[34] 2017
Zorro II 16-bit/7.14 MHz[35] 1986
ISA 16-Bit/8.33 MHz 1984 (created)
Europe Card Bus 8-Bit/10 MHz 1977 (created)
S-100 bus 8-bit/10 MHz 1976 (published)
Serial Peripheral Interface Bus (Up to 100 MHz) 1989
Low Pin Count [x] 2002
STEbus 8-Bit/16 MHz 1987 (standardized)
C-Bus 16-bit/10 MHz [36] 1982
HP Precision Bus
STD-32 32-bit/8 MHz [37]
NESA 32-bit/8 MHz [38]
EISA 32-bit/8.33 MHz 1988
VME64 32-64bit 1981
NuBus 10 MHz 1987 (standardized)
DEC TURBOchannel 32-bit/12.5 MHz
MCA 16-32bit/10 MHz 1987
NuBus90 20 MHz 1991
APbus 32-bit/25(?) MHz [39]
Sbus 32-bit/25 MHz 1989
DEC TURBOchannel 32-bit/25 MHz
Local Bus 98 32-bit/33 MHz [40]
VESA Local Bus (VLB) 32-bit/33 MHz 1992
PCI 32-bit/33 MHz 1993
Zorro III 32-bit/async (eq. 37.5 MHz)[41][42] [43] 1990
VESA Local Bus (VLB) 32-bit/40 MHz 1992
Sbus 64-bit/25 MHz 1995
PCI 64-bit/33 MHz 1993
PCI 32-bit/66 MHz 1995
AGP 1997
PCI Express 1.0 (×1 link)[44] [z] 2004
RapidIO Gen1 1×
HIO bus
GIO64 64-bit/40 MHz
PCI Express 1.0 (×2 link)[44] [z] 2011
PCI Express 2.0 (×1 link)[45] [z] 2007
AGP 2× 1997
PCI 64-bit/66 MHz
PCI-X DDR 16-bit
RapidIO Gen2 1×
PCI 64-bit/100 MHz
PCI Express 3.0 (×1 link)[46] [y] 2011
Unified Media Interface (UMI) (×4 link) [z] 2011
Direct Media Interface (DMI) (×4 link) [z] 2004
Enterprise Southbridge Interface (ESI)
PCI Express 1.0 (×4 link)[44] [z] 2004
PCI Express 2.0 (x2 link)[44] [z] 2007
AGP 4× 1998
PCI-X 133
PCI-X QDR 16-bit
InfiniBand single 4×[29] [z]
RapidIO Gen1 4×
RapidIO Gen2 2×
PCI Express 3.0 (×2 link)[46] [y] 2011
Unified Media Interface 2.0 (UMI 2.0; ×4 link) [z] 2012
Direct Media Interface 2.0 (DMI 2.0; ×4 link) [z] 2011
PCI Express 1.0 (×8 link)[44] [z] 2004
PCI Express 2.0 (×4 link)[45] [z] 2007
AGP 8× 2002
RapidIO Gen2 4×
Sun JBus (200 MHz) 2003
HyperTransport (800 MHz, 16-pair) 2001
PCI Express 3.0 (×4 link)[46] [y] 2011
HyperTransport (1 GHz, 16-pair)
PCI Express 1.0 (×16 link)[44] [z] 2004
PCI Express 2.0 (×8 link)[45] [z] 2007
AGP 8× 64-bit
RapidIO Gen2 8x
Direct Media Interface 3.0 (DMI 3.0; ×4 link) [z] 2015
PCI Express 3.0 (×8 link)[46] [y] 2011
PCI Express 1.0 (×32 link)[44] [z] 2001
PCI Express 2.0 (×16 link)[45] [z] 2007
RapidIO Gen2 16x
PCI Express 3.0 (×16 link)[46] [y] 2011
CAPI [y] 2014
PCI Express 2.0 (×32 link)[45] [z] 2007
QPI (4.80GT/s, 2.40 GHz)
HyperTransport 2.0 (1.4 GHz, 32-pair) 2004
QPI (5.86GT/s, 2.93 GHz)
QPI (6.40GT/s, 3.20 GHz)
QPI (7.2GT/s, 3.6 GHz) 2012
PCI Express 3.0 (×32 link)[46] [y] 2011
PCI Express 4.0 (×16 link)[47] [y] 2018
CAPI 2 [y] 2016
QPI (8.0GT/s, 4.0 GHz) 2012
QPI (9.6GT/s, 4.8 GHz) 2014
HyperTransport 3.0 (2.6 GHz, 32-pair) 2006
HyperTransport 3.1 (3.2 GHz, 32-pair) 2008
CXL Specification 1.x (×16 link) 2019
PCI Express 5.0 (×16 link)[48] [y] 2019
NVLink 1.0 2016
NVLink 2.0 2017
Infinity Fabric (Max theoretical) 2017

x LPC protocol includes high overhead. While the gross data rate equals 33.3 million 4-bit-transfers per second (or ), the fastest transfer, firmware read, results in . The next fastest bus cycle, 32-bit ISA-style DMA write, yields only . Other transfers may be as low as .[49]

y Uses 128b/130b encoding, meaning that about 1.54% of each transfer is used by the interface instead of carrying data between the hardware components at each end of the interface. For example, a single link PCIe 3.0 interface has an 8 Gbit/s transfer rate, yet its usable bandwidth is only about 7.88 Gbit/s.

z Uses 8b/10b encoding, meaning that 20% of each transfer is used by the interface instead of carrying data from between the hardware components at each end of the interface. For example, a single link PCIe 1.0 has a 2.5 Gbit/s transfer rate, yet its usable bandwidth is only 2 Gbit/s (250 MB/s).


Technology Rate Year
PC Card 16-bit 255 ns byte mode
PC Card 16-bit 255 ns word mode
PC Card 16-bit 100 ns byte mode
PC Card 16-bit 100 ns word mode
PC Card 32-bit (CardBus) byte mode
ExpressCard 1.2 USB 2.0 mode
PC Card 32-bit (CardBus) word mode
PC Card 32-bit (CardBus) doubleword mode
ExpressCard 1.2 PCI Express mode
ExpressCard 2.0 USB 3.0 mode
ExpressCard 2.0 PCI Express mode


Technology Rate Year
Teletype Model 33 paper tape 1963
TRS-80 Model 1 Level 1 BASIC cassette tape interface 1977
Apple 2 cassette tape interface 1977
Single Density 8-inch FM Floppy Disk Controller (160 KB) 1973
Double Density 5.25-inch MFM Floppy Disk Controller (360 KB) 1978
High Density MFM Floppy Disk Controller (1.2 MB/1.44 MB) 1984
CD Controller (1×) 1988
MFM hard disk 1980
RLL hard disk
DVD Controller (1×)
ATA PIO Mode 0 1986
HD DVD Controller (1×)
Blu-ray Controller (1×)
SCSI (Narrow SCSI) (5 MHz)[50] 1986
ATA PIO Mode 1 1994
ATA PIO Mode 2 1994
Fast SCSI (8 bits/10 MHz)
ATA PIO Mode 3 1996
AoE over Fast Ethernet[51] 2009
iSCSI over Fast Ethernet[52] 2004
ATA PIO Mode 4 1996
Fast Wide SCSI (16 bits/10 MHz)
Ultra SCSI (Fast-20 SCSI) (8 bits/20 MHz)
SD (High Speed)
Ultra DMA ATA 33 1998
Ultra Wide SCSI (16 bits/20 MHz)
Ultra-2 SCSI 40 (Fast-40 SCSI) (8 bits/40 MHz)
Ultra DMA ATA 66 2000
Blu-ray Controller (16×)
Ultra-2 wide SCSI (16 bits/40 MHz)
Serial Storage Architecture SSA 1990
Ultra DMA ATA 100 2002
Fibre Channel 1GFC (1.0625 GHz)[53] 1997
AoE over gigabit Ethernet, jumbo frames[54] 2009
iSCSI over gigabit Ethernet, jumbo frames[55] 2004
Ultra DMA ATA 133 2005
Ultra-3 SCSI (Ultra 160 SCSI; Fast-80 Wide SCSI) (16 bits/40 MHz DDR)
SATA revision 1.0[56] [a] 2003
Fibre Channel 2GFC (2.125 GHz)[53] 2001
Ultra-320 SCSI (Ultra4 SCSI) (16 bits/80 MHz DDR)
Serial Attached SCSI (SAS) SAS-1[56] [a] 2004
SATA Revision 2.0[56] [a] 2004
Fibre Channel 4GFC (4.25 GHz)[53] 2004
Serial Attached SCSI (SAS) SAS-2[56] [a] 2009
SATA Revision 3.0[56] [a] 2008
Fibre Channel 8GFC (8.50 GHz)[53] 2005
AoE over 10GbE[54] 2009
iSCSI over 10GbE[55] 2004
FCoE over 10GbE[57] 2009
Serial Attached SCSI (SAS) SAS-3[56] 2013
Fibre Channel 16GFC (14.025 GHz)[53] [b] 2011
SATA Express 2013
Serial Attached SCSI (SAS) 4 [c] 2017
UFS (version 3.0) 2018
Fibre Channel 32GFC (28.05 GHz)[53] [b] 2016
NVMe over M.2 or U.2 (using PCI Express 3.0 ×4 link)[46] 2013
iSCSI over InfiniBand 2007
iSCSI over 100G Ethernet[55] 2010
FCoE over 100G Ethernet[57] 2010

a Uses 8b/10b encoding b Uses 64b/66b encoding c Uses 128b/150b encoding


Technology Rate Year
Apple Desktop Bus 1986
PS/2 port 1987
Serial MIDI 1983
CBM Bus max[58][59] 1981
Serial RS-232 max 1962
Serial DMX512A 1998
Parallel (Centronics/IEEE 1284) 1970 (standardized 1994)
Serial 16550 UART max
USB 1.0 low speed 1996
Serial UART max
GPIB/HPIB (IEEE-488.1) IEEE-488 max. Late 1960s (standardized 1976)
Serial EIA-422 max.
USB 1.0 full speed 1996
Parallel (Centronics/IEEE 1284) EPP (Enhanced Parallel Port) 1992
Parallel (Centronics/IEEE 1284) ECP (Extended Capability Port) 1994
Serial EIA-485 max.
GPIB/HPIB (IEEE-488.1-2003) IEEE-488 max.
FireWire (IEEE 1394) 100 1995
FireWire (IEEE 1394) 200 1995
FireWire (IEEE 1394) 400 1995
USB 2.0 high speed 2000
FireWire (IEEE 1394b) 800[60] 2002
Fibre Channel 1 Gb SCSI
FireWire (IEEE 1394b) 1600[60] 2007
Fibre Channel 2 Gb SCSI
eSATA (SATA 300) 2004
CoaXPress Base (up and down bidirectional link) + 2009
FireWire (IEEE 1394b) 3200[60] 2007
External PCI Express 2.0 ×1
Fibre Channel 4 Gb SCSI
USB 3.0 SuperSpeed (aka USB 3.1 Gen 1) 2010
eSATA (SATA 600) 2011
CoaXPress full (up and down bidirectional link) + 2009
External PCI Express 2.0 ×2
USB 3.1 SuperSpeed+ (aka USB 3.1 Gen 2) 2013
External PCI Express 2.0 ×4
Thunderbolt 2 × 2 × 2011
USB 3.2 SuperSpeed+[61] (aka USB 3.2 Gen 2×2) 2017
Thunderbolt 2 2013
External PCI Express 2.0 ×8
Thunderbolt 3 two links 2015
USB 4.0[62] 2019
External PCI Express 2.0 ×16


Technology Rate Year
Media Independent Interface (MII; 4 lanes)
Reduced MII (RMII; 2 lanes)
Serial MII (SMII; 1 lane)
Gigabit MII (GMII; 8 lanes)
Reduced gigabit/s MII (RGMII; 4 lanes)
Serial gigabit/s MII (SGMII; 2 lanes)
Reduced serial gigabit/s MII (RSGMII; 2 lanes)
Reduced serial gigabit/s MII plus (RSGMII-PLUS; 2 lanes)
Quad serial gigabit/s MII (QSGMII; 2 lanes)
10 gigabit/s MII (XGMII; 32 lanes)
XGMII attachment unit interface (XAUI; 4 lanes)
40 gigabit/s MII (XLGMII)
100 gigabit/s MII (CGMII) 2008


Technology Rate Year
10 gigabit/s 16-bit interface (XSBI; 16 lanes)

Dynamic random-access memory

The table below shows values for PC memory module types. These modules usually combine multiple chips on one circuit board. SIMM modules connect to the computer via an 8-bit- or 32-bit-wide interface. RIMM modules used by RDRAM are 16-bit- or 32-bit-wide.[63] DIMM modules connect to the computer via a 64-bit-wide interface. Some other computer architectures use different modules with a different bus width.

In a single-channel configuration, only one module at a time can transfer information to the CPU. In multi-channel configurations, multiple modules can transfer information to the CPU at the same time, in parallel. FPM, EDO, SDR, and RDRAM memory was not commonly installed in a dual-channel configuration. DDR and DDR2 memory is usually installed in single- or dual-channel configuration. DDR3 memory is installed in single-, dual-, tri-, and quad-channel configurations. Bit rates of multi-channel configurations are the product of the module bit-rate (given below) and the number of channels.

Module type Chip type Internal clock[a] Bus clock Bus speed[b] Transfer rate
FPM DRAM 45 ns
EDO DRAM 30 ns
PC-66 SDR SDRAM 10/15 ns
PC-100 SDR SDRAM 8 ns
PC-133 SDR SDRAM 7/7.5 ns
RIMM-2100 RDRAM PC1066
RIMM-2400 RDRAM PC1200
PC2-3200 DDR2 SDRAM DDR2-400
PC2-4200 DDR2 SDRAM DDR2-533
PC2-5300 DDR2 SDRAM DDR2-667
PC2-6000 DDR2 SDRAM DDR2-750
PC2-6400 DDR2 SDRAM DDR2-800
PC3-6400 DDR3 SDRAM DDR3-800
PC2-7200 DDR2 SDRAM DDR2-900
PC2-8000 DDR2 SDRAM DDR2-1000
PC2-8500 DDR2 SDRAM DDR2-1066
PC3-8500 DDR3 SDRAM DDR3-1066
PC2-8800 DDR2 SDRAM DDR2-1100
PC2-9200 DDR2 SDRAM DDR2-1150
PC2-9600 DDR2 SDRAM DDR2-1200
PC2-10000 DDR2 SDRAM DDR2-1250
PC3-10600 DDR3 SDRAM DDR3-1333
PC3-11000 DDR3 SDRAM DDR3-1375
PC3-12800 DDR3 SDRAM DDR3-1600
PC3-13000 DDR3 SDRAM DDR3-1625
PC3-14400 DDR3 SDRAM DDR3-1800
PC3-14900 DDR3 SDRAM DDR3-1866
PC3-16000 DDR3 SDRAM DDR3-2000
PC3-17000 DDR3 SDRAM DDR3-2133
PC4-17000 DDR4 SDRAM DDR4-2133
PC3-17600 DDR3 SDRAM DDR3-2200
PC3-19200 DDR3 SDRAM DDR3-2400
PC4-19200 DDR4 SDRAM DDR4-2400
PC3-21300 DDR3 SDRAM DDR3-2666
PC4-21300 DDR4 SDRAM DDR4-2666
PC3-24000 DDR3 SDRAM DDR3-3000
PC4-24000 DDR4 SDRAM DDR4-3000
PC4-25600 DDR4 SDRAM DDR4-3200
PC5-41600 DDR5 SDRAM DDR5-5200
PC5-51200 DDR5 SDRAM DDR5-6400

a The clock rate at which DRAM memory cells operate. The memory latency is largely determined by this rate. Note that until the introduction of DDR4 the internal clock rate saw relatively slow progress. DDR/DDR2/DDR3 memory uses 2n/4n/8n (respectively) prefetch buffer to provide higher throughput, while the internal memory speed remains similar to that of the previous generation.

b The "memory speed/clock" advertised by manufactures and suppliers usually refers to this rate (with 1 GT/s = 1 GHz). Note that modern types of memory use DDR bus with two transfers per clock.

Graphics processing units' RAM

RAM memory modules are also utilised by graphics processing units; however, memory modules for those differ somewhat from standard computer memory, particularly with lower power requirements, and are specialised to serve GPUs: for example, GDDR3 was fundamentally based on DDR2. Every graphics memory chip is directly connected to the GPU (point-to-point). The total GPU memory bus width varies with the number of memory chips and the number of lanes per chip. For example, GDDR5 specifies either 16 or 32 lanes per "device" (chip), while GDDR5X specifies 64 lanes per chip. Over the years, bus widths rose from 64-bit to 512-bit and beyond: e.g. HBM is 1024 bits wide.[64] Because of this variability, graphics memory speeds are sometimes compared per pin. For direct comparison to the values for 64-bit modules shown above, video RAM is compared here in 64-lane lots, corresponding to two chips for those devices with 32-bit widths. In 2012, high-end GPUs used 8 or even 12 chips with 32 lanes each, for a total memory bus width of 256 or 384 bits. Combined with a transfer rate per pin of 5 GT/s or more, such cards could reach 240 GB/s or more.

RAM frequencies used for a given chip technology vary greatly. Where single values are given below, they are examples from high-end cards.[65] Since many cards have more than one pair of chips, the total bandwidth is correspondingly higher. For example, high-end cards often have eight chips, each 32 bits wide, so the total bandwidth for such cards is four times the value given below.

Module type Chip type Memory clock Transfers/s Transfer rate
64 lanes DDR
64 lanes DDR2
64 lanes GDDR3
64 lanes GDDR4
64 lanes GDDR5[66]
64 lanes GDDR5X[67]
64 lanes GDDR6
1024 lanes (8 channels @ 128 lanes ea) HBM[68]
1024 lanes (8 channels @ 128 lanes ea) HBM2[68][69]
1024 lanes (8 channels @ 128 lanes ea) HBM3[69]
128 lanes (8 links @ 16 lanes ea) HMC (internal)
64 lanes (4 links @ 16 lanes ea) HMC2 (internal)

Digital audio

Device Rate
CD Audio (16-bit PCM)
I²S @ 24bit/48 kHz
AES/EBU @ 24-bit/48 kHz
S/PDIF fs 48kHz
ADAT Lightpipe (Type I) 1.152 MB/s
Intel High Definition Audio rev. 1.0[70] outbound; 24 Mbit/s inbound outbound; 3 MB/s inbound

Digital video interconnects

Data rates given are from the video source (e.g., video card) to receiving device (e.g., monitor) only. Out of band and reverse signaling channels are not included.

Device Rate Year
Camera Link Base (single) 24-bit 85 MHz
LVDS Display Interface[71]
3G-SDI (SMPTE 424M) 2006
Single link DVI [a] 1999
HDMI 1.0[72] [a] 2002
Camera Link full (dual) 64-bit 85 MHz
6G-SDI (SMPTE 2081) 2015
DisplayPort 1.0 (4-lane Reduced Bit Rate)[73] [a] 2006
Dual link DVI [a] 1999
Thunderbolt 2 × 2 × 2011
HDMI 1.3[74] [a] 2006
Dual High-Speed LVDS Display Interface
DisplayPort 1.0 (4-lane High Bit Rate)[73] [a] 2006
12G-SDI (SMPTE 2082) 2015
HDMI 2.0[75] [a] 2013
Thunderbolt 2 2013
DisplayPort 1.2 (4-lane High Bit Rate 2)[73] [a] 2009
DisplayPort 1.3 (4-lane High Bit Rate 3) [a] 2014 (2016)
superMHL 2015
Thunderbolt 3 2015
HDMI 2.1[76] [b] 2017
DisplayPort 2.0 (4-lane) [c] 2019

a Uses 8b/10b encoding (20% coding overhead) b Uses 16b/18b encoding (11% overhead) c Uses 128b/132b encoding (3% overhead)

See also


  1. ^ NIST-Enhanced-WWVB-Broadcast-Format-sept-2012-Radio-Station-staff, By John Lowe, September 2012,
  2. ^[dead link]Archived version
  3. ^ TTY uses a Baudot code, not ASCII. This uses 5 bits per character instead of 8, plus one start and approx. 1.5 stop bits (7.5 total bits per character sent).
  4. ^ Morse can transport 26 alphabetic, 10 numeric and one interword gap plaintext symbols. Transmitting 37 different symbols requires 5.21 bits of information (25.21=37). A skilled operator encoding the benchmark "PARIS" plus an interword gap (equal to 31.26 bits) at 40 wpm is operating at an equivalence of 20.84 bit/s.
  5. ^ WPM, or Words Per Minute, is the number of times the word "PARIS" is transferred per minute. Strictly speaking the code is quinary, accounting inter-element, inter-letter, and inter-word gaps, yielding 50 binary elements (bits) per one word. Counting characters, including inter-word gaps, gives six characters per word or 240 characters per minute, and finally four characters per second.
  6. ^ a b c d e f g h i j All modems are wrongly assumed to be in serial operation with 1 start bit, 8 data bits, no parity, and 1 stop bit (2 stop bits for 110-baud modems). Therefore, currently modems are wrongly calculated with transmission of 10 bits per 8-bit byte (11 bits for 110-baud modems). Although the serial port is nearly always used to connect a modem and has equivalent data rates, the protocols, modulations and error correction differ completely.
  7. ^ a b Modem Types and Timeline, Daxal Communications, 2003-12-16, archived from the original on 2008-10-08, retrieved
  8. ^ a b c d e f g "ITU-T Recommendations: V Series: Data communication over the telephone network". ITU.
  9. ^ a b c 56K modems: V.90 and V.92 have just 5% overhead for the protocol signalling. The maximum capacity can only be achieved when the upstream (service provider) end of the connection is digital, i.e. a DS0 channel.
  10. ^ Note that effective aggregate bandwidth for an ISDN installation is typically higher than the rates shown for a single channel due to the use of multiple channels. A basic rate interface (BRI) provides two "B" channels and one "D" channel. Each B channel provides 64 kBit/s bandwidth and the "D" channel carries signaling (call setup) information. B channels can be bonded to provide a 128 kbit/s data rate. Primary rate interfaces (PRI) vary depending on whether the region uses E1 (Europe, world) or T1 (North America) bearers. In E1 regions, the PRI carries 30 B-channels and one D-channel; in T1 regions the PRI carries 23 B-channels and one D-channel. The D-channel has different bandwidth on the two interfaces.
  11. ^ Massey, David (2006-07-04), "Timeline of Telecommunications", Telephone Tribute, retrieved
  12. ^
  13. ^ "Recommendation G.991.1 (10/98)". ITU.
  14. ^ a b DOCSIS 1.0 Archived 2006-06-13 at the Wayback Machine includes technology which first became available around 1995-1996, and has since become very widely deployed. DOCSIS 1.1 Archived 2006-06-13 at the Wayback Machine introduces some security improvements and Quality of Service (QoS).
  15. ^ a b DOCSIS 2.0 Archived 2009-09-04 at the Wayback Machine specifications provide increased upstream throughput for symmetric services.
  16. ^ "G.983.2". ITU.
  17. ^ a b DOCSIS 3.0 Archived 2006-06-19 at the Wayback Machine includes support for channel bonding and IPv6.
  18. ^ "G.984.4 : Gigabit-capable passive optical networks (G-PON)". ITU.
  19. ^ DOCSIS 3.1 is currently in development by the Cablelabs Consortium
  20. ^ "G.987 : 10-Gigabit-capable passive optical network (XG-PON) systems". ITU.
  21. ^ "G.989 : 40-Gigabit-capable passive optical networks (NG-PON2)". ITU.
  22. ^ Most operators only support up to 9600bit/s
  23. ^ SDSL is available in various speeds.
  24. ^ ADSL connections will vary in throughput from 64 kbit/s to several Mbit/s depending on configuration. Most are commonly below 2 Mbit/s. Some ADSL and SDSL connections have a higher digital bandwidth than T1 but their rate is not guaranteed, and will drop when the system gets overloaded, whereas the T1 type connections are usually guaranteed and have no contention ratios.
  25. ^ Satellite internet may have a high bandwidth but also has a high latency due to the distance between the modem, satellite and hub. One-way satellite connections exist where all the downstream traffic is handled by satellite and the upstream traffic by land-based connections such as 56K modems and ISDN.
  26. ^ a b "MoCA 1.1 improves throughput" over coaxial cable to 175 Mbits/s versus the 100 Mbits/s provided by the MoCA 1.0 specification.
  27. ^ FireWire natively supports TCP/IP, and is often used at an alternative to Ethernet when connecting 2 nodes.
  28. ^ Data rate comparison between FW and Giganet shows that FW's lower overhead has nearly the same throughput as Giganet. Archived 2008-02-07 at the Wayback Machine
  29. ^ a b c d e f g h i j InfiniBand SDR, DDR and QDR use an 8b/10b encoding scheme.
  30. ^ a b c d e f g h i j k l InfiniBand FDR-10, FDR and EDR use a 64b/66b encoding scheme.
  31. ^ a b c Lee, Bill. "Chair of marketing working group". IBTA Blog. IBTA. Archived from the original on 2018-06-25. Retrieved 2018.
  32. ^ Mac History
  33. ^ VAW: Apple IIgs Specs Archived 2011-01-10 at the Wayback Machine
  34. ^ "After 35 years of I2C, I3C Improves Capability and Performance | Sensors and MEMS". Retrieved .
  35. ^ The Zorro II bus use 4 clocks per 16-Bit of data transferred. See the Zorro III technical specification for more information.
  36. ^ Japan resource article, Bus used in early NEC PC-9800 series and compatible systems
  37. ^ STD 32 Bus Specification and Designer's Guide
  38. ^ Japan resource article, Bus used in later NEC PC-9800 series and compatible systems
  39. ^ Local Area Networks Newsletter by Paul Polishuk, September 1992, Page 7 (APbus used in Sony NeWS and NEC UP4800 workstations and NEC EWS4800 servers after VMEbus and before switch to PCI)
  40. ^ Japan resource article, Bus used in NEC PC-9821 series
  41. ^ Dave Haynie, designer of the Zorro III bus, claims in this posting that the theoretical max of the Zorro III bus can be derived by the timing information given in chapter 5 of the Zorro III technical specification.
  42. ^ Dave Haynie, designer of the Zorro III bus, states in this posting that Zorro III is an asynchronous bus and therefore does not have a classical MHz rating. A maximum theoretical MHz value may be derived by examining timing constraints detailed in the Zorro III technical specification, which should yield about 37.5 MHz. No existing implementation performs to this level.
  43. ^ Dave Haynie, designer of the Zorro III bus, claims in this posting that Zorro III has a max burst rate of 150 MB/s.
  44. ^ a b c d e f g Note that PCI Express 1.0/2.0 lanes use an 8b/10b encoding scheme.
  45. ^ a b c d e PCIe 2.0 effectively doubles the bus standard's bandwidth from 2.5 GT/s to 5 GT/s
  46. ^ a b c d e f g PCIe 3.0 increases the bandwidth from 5 GT/s to 8 GT/s and switches to 128b-130b encoding
  47. ^ Born, Eric (8 June 2017). "PCIe 4.0 specification finally out with 16 GT/s on tap". Tech Report. Retrieved 2018.
  48. ^ Smith, Ryan. "PCI-SIG Finalizes PCIe 5.0 Specification: x16 Slots to Reach 64GB/sec". Retrieved .
  49. ^ Intel LPC Interface Specification 1.1
  50. ^ SCSI-1, SCSI-2 and SCSI-3 are signaling protocols and do not explicitly refer to a specific rate. Narrow SCSI exists using SCSI-1 and SCSI-2. Higher rates use SCSI-2 or later.
  51. ^ minimum overhead is 38 byte L1/L2, 14 byte AoE per 1024 byte user data
  52. ^ minimum overhead is 38 byte L1/L2, 20 byte IP, 20 byte TCP per 1460 byte user data
  53. ^ a b c d e f Fibre Channel 1GFC, 2GFC, 4GFC use an 8b/10b encoding scheme. Fibre Channel 10GFC, which uses a 64B/66B encoding scheme, is not compatible with 1GFC, 2GFC and 4GFC, and is used only to interconnect switches.
  54. ^ a b minimum overhead is 38 byte L1/L2, 14 byte AoE per 8192 byte user data
  55. ^ a b c minimum overhead is 38 byte L1/L2, 20 byte IP, 20 byte TCP per 8960 byte user data
  56. ^ a b c d e f SATA and SAS use an 8b/10b encoding scheme.
  57. ^ a b minimum overhead is 38 byte L1/L2, 36 byte FC per 2048 byte user data
  58. ^ proprietary serial version of IEEE-488 by Commodore International
  59. ^
  60. ^ a b c FireWire (IEEE 1394b) uses an 8b/10b encoding scheme.
  61. ^ Dent, Steve (26 July 2017). "USB 3.2 doubles your connection speeds with the same port". Engadget. Retrieved 2017.
  62. ^ Shilov, Anton. "USB4 Specification Announced: Adopting Thunderbolt 3 Protocol for 40 Gbps USB". Retrieved .
  63. ^ "RDRAM Memory Architecture".
  64. ^ Comparison of AMD graphics processing units
  65. ^ Comparison of Nvidia graphics processing units
  68. ^ a b Shilov, Anton (20 January 2016). "JEDEC Publishes HBM2 Specification". Anandtech. Retrieved 2017.
  69. ^ a b Walton, Mark (23 August 2016). "HBM3: Cheaper, up to 64GB on-package, and terabytes-per-second bandwidth". Ars Technica. Retrieved 2017.
  70. ^ High Definition Audio Specification, Revision 1.0a, 2010
  71. ^, Panel display interfaces and bandwidth: From TTL, LVDS, TDMS to DisplayPort
  72. ^ "". Archived from the original on 2008-12-05. Retrieved .
  73. ^ a b c Displayport Technical Overview Archived 2011-07-26 at the Wayback Machine, May 2010
  74. ^
  75. ^
  76. ^

External links

  This article uses material from the Wikipedia page available here. It is released under the Creative Commons Attribution-Share-Alike License 3.0.



Music Scenes